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integrated circuit systems, inc. ics9248-138 0342c?08/26/03 block diagram recommended application: 810/810e and solano type chipset. output features: 2- cpus @ 2.5v 9 - sdram @ 3.3v, including 1 free running 7 - pciclk @ 3.3v 1 - ioapic @ 2.5v, 3 - 3v66mhz @ 3.3v 2 - 48mhz, @ 3.3v fixed. 1 - 24/48mhz, @3.3v selectable by i 2 c 1 - ref @v3.3v, 14.318mhz. features: up to 200mhz frequency support support fs0-fs4 strapping status bit for i 2 c read back. support power management: through power down mode from i 2 c programming. spread spectrum for emi control ( 0.25% center). uses external 14.318mhz crystal skew specifications: cpu ? cpu: <175ps sdram - sdram: < 250ps 3v66 ? 3v66: <175ps pci ? pci: <500ps for group skew specifications, please refer to group timing relationship. functionality pin configuration 48-pin 300mil ssop * these inputs have a 120k pull up to vdd. ** these inputs have a 120k pull down to gnd. 1 these are double strength. 1 1 1 *sel24_48#/ref0 vddref x1 x2 gndref gnd3v66 3v66-0 3v66-1 3v66-2 vdd3v66 vddpci *fs0/pciclk0 **fs1/pciclk1 gndpci pciclk2 pciclk3 pciclk4 vddpci pciclk5 pciclk6 gndpci pd# sclk s data vddlapic ioapic vddlcpu cpuclk0 cpuclk1 gndlcpu gndsdr sdram0 sdram1 sdram2 vddsdr sdram3 sdram4 sdram5 gndsdr sdram6 sdram7 sdram_f vddsdr gnd48 24_48mhz/fs2** 48mhz/fs3* 48mhz/fs4* vdd48 1 1 ics9248-138 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 sel24_48# pll2 pll1 spread spectrum 48mhz [1:0] 24_48mhz cpuclk [1:0] 2 3 2 8 7 sdram [7:0] ioapic pciclk [6:0] sdram_f 3v66 [2:0] x1 x2 xtal osc cpu divder sdram divder ioapic divder pci divder 3v66 divder s data sclk fs[4:0] pd# control logic config. reg. / 2 ref0 frequency generator & integrated buffers for celeron & p ii / iii ? additional frequencies selectable through i 2 c programming. 4 s f3 s f2 s f1 s f0 s f u p c ) z h m ( m a r d s ) z h m ( 6 6 v 3 ) z h m ( k l c i c p ) z h m ( c i p a o i ) z h m ( 0000 0 7 6 . 6 60 0 . 0 0 17 6 . 6 63 3 . 3 37 6 . 6 1 0000 1 7 8 . 6 60 3 . 0 0 17 8 . 6 63 4 . 3 32 7 . 6 1 00010 7 6 . 8 60 0 . 3 0 17 6 . 8 63 3 . 4 36 1 . 7 1 0001 1 4 3 . 1 70 0 . 7 0 14 3 . 1 76 6 . 5 33 8 . 7 1 0010 0 0 0 . 0 0 10 0 . 0 0 17 6 . 6 63 3 . 3 37 6 . 6 1 0010 1 0 3 . 0 0 10 3 . 0 0 17 8 . 6 63 4 . 3 32 7 . 6 1 00110 0 0 . 3 0 10 0 . 3 0 17 6 . 8 63 3 . 4 37 1 . 7 1 0011 1 0 0 . 7 0 10 0 . 7 0 14 3 . 1 76 6 . 5 34 8 . 7 1 01000 3 3 . 3 3 13 3 . 3 3 17 6 . 6 63 3 . 3 37 6 . 6 1 0100 1 3 7 . 3 3 13 7 . 3 3 17 8 . 6 63 4 . 3 32 7 . 6 1 01010 3 3 . 7 3 13 3 . 7 3 17 6 . 8 63 3 . 4 37 1 . 7 1 01011 0 0 . 0 2 10 0 . 0 2 10 0 . 0 60 0 . 0 30 0 . 5 1 01100 3 3 . 3 3 10 0 . 0 0 17 6 . 6 63 3 . 3 37 6 . 6 1 0110 1 3 7 . 3 3 10 3 . 0 0 17 8 . 6 63 4 . 3 32 7 . 6 1 01110 3 3 . 7 3 10 0 . 3 0 17 6 . 8 63 3 . 4 37 1 . 7 1 01111 0 0 . 0 2 10 0 . 0 90 0 . 0 60 0 . 0 30 0 . 5 1 11010 0 0 . 0 6 10 0 . 0 6 10 0 . 0 80 0 . 0 40 0 . 0 2 1110 1 0 0 . 0 6 10 0 . 0 2 10 0 . 0 80 0 . 0 40 0 . 0 2 1101 1 7 6 . 6 6 17 6 . 6 6 14 3 . 3 87 6 . 1 44 8 . 0 2 11110 7 6 . 6 6 10 0 . 5 2 14 3 . 3 87 6 . 1 44 8 . 0 2
2 ics9248-138 0342c?08/26/03 general description pin configuration the ics9248-138 is the single chip clock solution for designs using the 810/810e and solano style chipset. it provides all necessary clock signals for such a system. spread spectrum may be enabled through i 2 c programming. spread spectrum typically reduces system emi by 8db to 10db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9248-138 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. serial programming i 2 c interface allows changing functions, stop clock programming and frequency selection. pin number pin name type description sel24_48mhz# in logic inputs frequency select i/o/usb output, when a "0" is latched, output frequency = 48mhz when a "1" is latched, output frequenc y = 24mhz ref0 out 14.318 mhz reference clock. 2, 10, 11, 18, 25, 30, 38 vdd pwr 3.3v power supply for sdram output buffers, pci output buffers, reference output buffers and 48mhz output 3 x1 in crystal input,nominally 14.318mhz. 4 x2 out crystal output, nominally 14.318mhz. 5, 6, 14, 21, 29, 34, 42 gnd pwr ground pin for 3v outputs. 9, 8, 7 3v66 [2:0] out 3.3v clocks fs0 in frequency select pin. pciclk0 out pci clock output fs1 in frequency select pin. pciclk1 out pci clock output 20, 19, 17, 16, 15 pciclk [6:2] out pci clock outputs. 22 pd# in asynchronous active low input pin used to power down the device into a low power state. the internal clocks are disabled and the vco and the crystal are stopped. the latency of the power down will not be greater than 3ms. 23 sclk in clock input of i2c input, 5v tolerant input 24 sdata in data input for i2c serial input, 5v tolerant input fs4 in frequency select pin. 48mhz out 48mhz output clocks fs3 in frequency select pin. 48mhz out 48mhz output clocks fs2 in frequency select pin. 24_48mhz out 24 or 48mhz output 31 sdram_f out free running sdram - used for feed back to chipset, should remain on always. 32, 33, 35, 36, 37, 39, 40, 41, sdram [7:0] out sdram clock outputs 43 gndlcpu pwr ground pin for the cpu clo cks. 44, 45 cpuclk [1:0] out cpu clock outputs. 46 vddlcpu pwr power pin for the cpuclks. 2.5v 47 ioapic out 2.5v clock output 48 vddlapic pwr power pin for the ioapic. 2.5v 1 26 28 12 13 27
3 ics9248-138 0342c?08/26/03 byte0: functionality and frequency select register (default = 0) serial configuration command bitmap note 1 : default at power-up will be for latched logic inputs to define frequency, as displayed by bit 3. i 2 c is a trademark of philips corporation t i bn o i t p i r c s e dd w p t i b 4 : 7 , 2 2 t i b7 t i b6 t i b5 t i b4 t i b - l c u p c k ) z h m ( m a r d s ) z h m ( 6 6 v 3 ) z h m ( k l c i c p ) z h m ( c i p a o i ) h m ( e g a t n e c e r p d a e r p s ) 1 0 0 0 , 0 ( 4 s f3 s f2 s f1 s f0 s f 00000 7 6 . 6 60 0 . 0 0 17 6 . 6 63 3 . 3 37 6 . 6 1d a e r p s n w o d % 5 . 0 - o t 0 0000 1 7 8 . 6 60 3 . 0 0 17 8 . 6 63 4 . 3 32 7 . 6 1d a e r p s r e t n e c % 5 2 . 0 000 10 7 6 . 8 60 0 . 3 0 17 6 . 8 63 3 . 4 36 1 . 7 1d a e r p s r e t n e c % 5 2 . 0 000 11 4 3 . 1 70 0 . 7 0 14 3 . 1 77 6 . 5 33 8 . 7 1d a e r p s r e t n e c % 5 2 . 0 00100 0 0 . 0 0 10 0 . 0 0 17 6 . 6 63 3 . 3 37 6 . 6 1d a e r p s n w o d % 5 . 0 - o t 0 0010 1 0 3 . 0 0 10 3 . 0 0 17 8 . 6 63 4 . 3 32 7 . 6 1d a e r p s r e t n e c % 5 2 . 0 00110 0 0 . 3 0 10 0 . 3 0 17 6 . 8 63 3 . 4 37 1 . 7 1d a e r p s r e t n e c % 5 2 . 0 00111 0 0 . 7 0 10 0 . 7 0 14 3 . 1 77 6 . 5 34 8 . 7 1d a e r p s r e t n e c % 5 2 . 0 01000 3 3 . 3 3 13 3 . 3 3 17 6 . 6 63 3 . 3 37 6 . 6 1d a e r p s n w o d % 5 . 0 - o t 0 01001 3 7 . 3 3 13 7 . 3 3 17 8 . 6 63 4 . 3 32 7 . 6 1d a e r p s r e t n e c % 5 2 . 0 01010 3 3 . 7 3 13 3 . 7 3 17 6 . 8 63 3 . 4 37 1 . 7 1d a e r p s r e t n e c % 5 2 . 0 01011 0 0 . 0 2 10 0 . 0 2 10 0 . 0 60 0 . 0 30 0 . 5 1d a e r p s r e t n e c % 5 2 . 0 01100 3 3 . 3 3 10 0 . 0 0 17 6 . 6 63 3 . 3 37 6 . 6 1d a e r p s n w o d % 5 . 0 - o t 0 01101 3 7 . 3 3 10 3 . 0 0 17 8 . 6 63 4 . 3 32 7 . 6 1d a e r p s r e t n e c % 5 2 . 0 01110 3 3 . 7 3 10 0 . 3 0 17 6 . 8 63 3 . 4 37 1 . 7 1d a e r p s r e t n e c % 5 2 . 0 01111 0 0 . 0 2 10 0 . 0 90 0 . 0 60 0 . 0 30 0 . 5 1d a e r p s r e t n e c % 5 2 . 0 100 0 0 0 0 . 6 3 10 0 . 6 3 10 0 . 8 60 0 . 4 30 0 . 7 1d a e r p s r e t n e c % 5 2 . 0 100 0 1 0 0 . 0 4 10 0 . 0 4 10 0 . 0 70 0 . 5 30 5 . 7 1d a e r p s r e t n e c % 5 2 . 0 100 10 7 6 . 2 4 17 6 . 2 4 14 3 . 1 77 6 . 5 34 8 . 7 1d a e r p s r e t n e c % 5 2 . 0 100 1 1 3 3 . 5 4 13 3 . 5 4 17 6 . 2 73 3 . 6 37 1 . 8 1d a e r p s r e t n e c % 5 2 . 0 10 10 0 0 0 . 6 3 10 0 . 2 0 10 0 . 8 60 0 . 4 30 0 . 7 1d a e r p s r e t n e c % 5 2 . 0 10 10 1 0 0 . 0 4 10 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 1d a e r p s r e t n e c % 5 2 . 0 10 1 10 7 6 . 2 4 10 0 . 7 0 14 3 . 1 77 6 . 5 34 8 . 7 1d a e r p s r e t n e c % 5 2 . 0 10 1 1 1 3 3 . 5 4 10 0 . 9 0 17 6 . 2 73 3 . 6 37 1 . 8 1d a e r p s r e t n e c % 5 2 . 0 11000 7 6 . 6 4 17 6 . 6 4 14 3 . 3 77 6 . 6 34 3 . 8 1d a e r p s r e t n e c % 5 2 . 0 1100 1 3 3 . 3 5 13 3 . 3 5 17 6 . 6 73 3 . 8 37 1 . 9 1d a e r p s r e t n e c % 5 2 . 0 110 10 0 0 . 0 6 10 0 . 0 6 10 0 . 0 80 0 . 0 40 0 . 0 2d a e r p s r e t n e c % 5 2 . 0 110 11 7 6 . 6 6 17 6 . 6 6 14 3 . 3 87 6 . 1 44 8 . 0 2d a e r p s r e t n e c % 5 2 . 0 11100 7 6 . 6 4 10 0 . 0 1 14 3 . 3 77 6 . 6 34 3 . 8 1d a e r p s r e t n e c % 5 2 . 0 1110 1 0 0 . 0 6 10 0 . 0 2 10 0 . 0 80 0 . 0 40 0 . 0 2d a e r p s r e t n e c % 5 2 . 0 11110 7 6 . 6 6 10 0 . 5 2 14 3 . 3 87 6 . 1 44 8 . 0 2d a e r p s r e t n e c % 5 2 . 0 11111 0 0 . 0 0 20 0 . 0 0 27 6 . 6 63 3 . 3 37 6 . 6 1d a e r p s r e t n e c % 5 2 . 0 3 t i b s t u p n i d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 4 : 6 , 2 t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 1 t i b l a m r o n - 0 d a e r p s r e t n e c % 5 2 . 0 d e l b a n e m u r t c e p s d a e r p s - 1 0 0 t i b g n i n n u r - 0 s t u p t u o l l a e t a t s i r t - 1 0
4 ics9248-138 0342c?08/26/03 byte 1: sdram control register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-x# 2 s f 6 t i b-x# 1 s f 5 t i b1 31 f _ m a r d s 4 t i b2 31 7 m a r d s 3 t i b3 31 6 m a r d s 2 t i b5 31 5 m a r d s 1 t i b6 31 4 m a r d s 0 t i b7 31 3 m a r d s byte 4: control register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b-1 d e v r e s e r 5 t i b-1 d e v r e s e r 4 t i b-1 d e v r e s e r 3 t i b-1 d e v r e s e r 2 t i b7 21 0 - z h m 8 4 1 t i b6 21 1 - z h m 8 4 0 t i b8 21 z h m 8 4 _ 4 2 byte 3: 3v66, control register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-x# 4 s f 6 t i b-1 d e v r e s e r 5 t i b-1 d e v r e s e r 4 t i b-1 d e v r e s e r 3 t i b-1 d e v r e s e r 2 t i b71 0 - 6 6 v 3 1 t i b81 1 - 6 6 v 3 0 t i b91 2 - 6 6 v 3 byte 2: pci, control register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-x# 0 s f 6 t i b0 21 6 k l c i c p 5 t i b9 11 5 k l c i c p 4 t i b7 11 4 k l c i c p 3 t i b6 11 3 k l c i c p 2 t i b5 11 2 k l c i c p 1 t i b3 11 1 k l c i c p 0 t i b2 11 0 k l c i c p notes: 1. inactive means outputs are held low and are disabled from switching. 2. latched frequency selects (fs#) will be inverted logic load of the input frequency select pin conditions. byte 5: control register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-x # ) # 8 4 _ 4 2 l e s ( 6 t i b110 f e r 5 t i b7 41 c i p a o i 4 t i b4 41 1 k l c u p c 3 t i b5 41 0 k l c u p c 2 t i b9 31 2 m a r d s 1 t i b0 41 1 m a r d s 0 t i b1 41 0 m a r d s t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 ) e t o n ( d e v r e s e r 6 t i b-0 ) e t o n ( d e v r e s e r 5 t i b-0 ) e t o n ( d e v r e s e r 4 t i b-0 ) e t o n ( d e v r e s e r 3 t i b-0 ) e t o n ( d e v r e s e r 2 t i b-1 ) e t o n ( d e v r e s e r 1 t i b-1 ) e t o n ( d e v r e s e r 0 t i b-0 ) e t o n ( d e v r e s e r byte 6: control register (1= enable, 0 = disable) note: don?t write into this register, writing into this register can cause malfunction. this byte becomes the byte count for readback, so it cannot be seen as data.
5 ics9248-138 0342c?08/26/03 electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v + 5%, vddl=2.5 v+ 5%(unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v input high current i ih v in = v dd -5 5 ma input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 ma input low current i il2 v in = 0 v; inputs with pull-up resistors -200 ma operating i dd3. 3op c l = 0 pf; select @ 66m 100 ma supply current power down i dd3. 3pd c l = 0 pf; with input address to vdd or gnd 600 ma supply current input frequency f i v dd = 3.3 v; 14.318 mhz pin inductance l p in 7nh input capacitance 1 c in logic inputs 5 pf c out out put pin capacitance 6 pf c inx x1 & x2 pins 27 45 pf transition time 1 t trans to 1st crossing of target freq. 3 ms settling time 1 t s from 1st crossing to 1% target freq. 3 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms delay t pzh ,t pzh output enable delay (all outputs) 1 10 ns t plz ,t pzh output disable delay (all outputs) 1 10 ns 1 guaranteed by desi g n, not 100% tested in production. group timing relationship table absolute maximum ratings core supply voltage . . . . . . . . . . . . . . . . . . . . 5.5 v i/o supply voltage . . . . . . . . . . . . . . . . . . . . . . 3.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. p u o r gz h m 6 6 u p c z h m 0 0 1 m a r d s z h m 0 0 1 u p c z h m 0 0 1 m a r d s z h m 3 3 1 u p c z h m 0 0 1 m a r d s z h m 3 3 1 u p c z h m 3 3 1 m a r d s t e s f f oe c n a r e l o tt e s f f oe c n a r e l o tt e s f f oe c n a r e l o tt e s f f oe c n a r e l o t m a r d s o t u p cs n 5 . 2s p 0 0 5s n 0 . 5s p 0 0 5s n 0 . 0s p 0 0 5s n 5 7 . 3s p 0 0 5 6 6 v 3 o t u p cs n 5 . 7s p 0 0 5s n 0 . 5s p 0 0 5s n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5 6 6 v 3 o t m a r d ss n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5s n 5 7 . 3s p 0 0 5 i c p o t 6 6 v 3s n 5 . 3 - 5 . 1s p 0 0 5s n 5 . 3 - 5 . 1s p 0 0 5s n 5 . 3 - 5 . 1s p 0 0 5s n 5 . 3 - 5 . 1s p 0 0 5 i c p o t i c ps n 0 . 0s n 0 . 1s n 0 . 0s n 0 . 1s n 0 . 0s n 0 . 1s n 0 . 0s n 0 . 1 t o d & b s uh c n y s aa / nh c n y s aa / nh c n y s aa / nh c n y s aa / n
6 ics9248-138 0342c?08/26/03 electrical characteristics - 3v66 t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp1 1 v o = v dd *(0.5) 12 55 ? output impedance r dsn1 1 v o = v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v output high current i oh1 voh@ min = 1.0 v, voh@ max = 3.135 v -33 -33 ma output low current i ol1 vol@ min = 1.95 v, vol@ max= 0.4 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns duty cycle d t1 1 v t = 1.5 v 45 55 % skew t sk1 1 v t = 1.5 v 175 ps jitter t jcyc-cyc v t = 1.5 v 500 ps 1 guaranteed b y desi g n, not 100% tested in production. electrical characteristics - cpu t a = 0 - 70c, v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp2b 1 v o = v dd *(0.5) 13.5 45 ? output impedance r dsn2b 1 v o = v dd *(0.5) 13.5 45 ? output high voltage v oh2b i oh = -1 ma 2 v output low voltage v ol2b i ol = 1 ma 0.4 v output high current i oh2b v oh @min = 1.0v , v oh@ max = 2.375v -27 -27 ma output low current i ol2b v ol @min = 1.2v , v ol@ max = 0.3v 27 30 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 0.4 1.6 ns fall time t f2b 1 v oh = 0.4 v, v ol = 2.0 v 0.4 1.6 ns duty cycle d t2b 1 v t = 1.25 v 45 55 % skew t sk2b 1 v t = 1.25 v 250 ps jitter t jcyc-cyc 1 v t = 1.25 v 250 ps 1 guaranteed by design, not 100% tested in production.
7 ics9248-138 0342c?08/26/03 electrical characteristics - sdram t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 20 - 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp3 1 v o = v dd *(0.5) 10 24 ? output impedance r dsn3 1 v o = v dd *(0.5) 10 24 ? output high voltage v oh3 i oh = -1 ma 2.4 v output low voltage v ol3 i ol = 1 ma 0.4 v output high current i oh3 v oh @min = 2.0 v, v oh@ max =3.135 v -54 -46 ma output low current i ol3 v ol@ min = 1.0 v, v ol@ max =0.4 v 54 53 ma rise time t r3 1 v ol = 0.4 v, v oh = 2.4 v 0.4 1.6 ns fall time t f3 1 v oh = 2.4 v, v ol = 0.4 v 0.4 1.6 ns duty cycle d t3 1 v t = 1.5 v 45 55 % skew t sk3 1 v t = 1.5 v 250 ps jitter t j cyc-cyc v t = 1.5 v 250 ps 1 guaranteed b y desi g n, not 100% tested in production. electrical characteristics - ioapic t a = 0 - 70c;v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp4b 1 v o = v dd *(0.5) 9 30 ? output impedance r dsn4b 1 v o = v dd *(0.5) 9 30 ? output high voltage v oh4\b i oh = -5.5 ma 2 v output low voltage v ol4b i ol = 9.0 ma 0.4 v output high current i oh4b v oh@ min = 1.0 v, v oh@ max = 2.375 v -27 -27 ma output low current i ol4b v ol@ min = 1.2 v, v ol@ max= 0.3 v 27 30 ma rise time t r4b 1 v ol = 0.4 v, v oh = 2.0 v 0.4 1.6 ns fall time t f4b 1 v oh = 2.0 v, v ol = 0.4 v 0.4 1.6 ns duty cycle d t4b 1 v t = 1.25 v 45 55 % skew t sk4 1 250 ps jitter t jcyc-cyc v t = 1.25 v 500 ps 1 guaranteed by design, not 100% tested in production.
8 ics9248-138 0342c?08/26/03 electrical characteristics - pci t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp1 1 v o = v dd *(0.5) 12 55 ? output impedance r dsn1 1 v o = v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v output high current i oh1 voh@ min = 1.0 v, voh@ max = 3.13 5 -33 -33 ma output low current i ol1 vol@ min = 1.95 v, vol@ max= 0.4 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns duty cycle d t1 1 v t = 1.5 v 45 55 % skew t sk1 1 v t = 1.5 v 500 ps jitter t jcyc-cyc v t = 1.5 v 500 ps 1 guaranteed b y desi g n, not 100% tested in production. electrical characteristics - ref, 48mhz_0 t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 10 -20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp5 1 v o = v dd *(0.5) 20 60 ? output impedance r dsn5 1 v o = v dd *(0.5) 20 60 ? output high voltage v oh5 i oh = 1 ma 2.4 v output low voltage v ol5 i ol = -1 ma 0.4 v output high current i oh5 v oh @min =1 v, v oh@max = 3.135 v -29 -23 ma output low current i ol5 v ol@min =1.95 v, v ol@min =0.4 v 29 27 ma rise time t r5 1 v ol = 0.4 v, v oh = 2.4 v 4 ns fall time t f5 1 v oh = 2.4 v, v ol = 0.4 v 4 ns duty cycle d t5 1 v t = 1.5 v 45 55 % skew t sk v t = 1.5 v 250 ps t j c y c-c y c 1 v t = 1.5 v; fixed clocks 500 ps t jcyc-cyc 1 v t = 1.5 v; ref clocks 1000 ps 1 guaranteed by design, not 100% tested in production. jitter
9 ics9248-138 0342c?08/26/03 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends a dummy command code ics clock will acknowledge controller (host) sends a dummy byte count ics clock will acknowledge controller (host) starts sending first byte (byte 0) through byte 5 ics clock will acknowledge each byte one at a time . controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the byte count controller (host) acknowledges ics clock sends first byte (byte 0) through byte 5 controller (host) will need to acknowledge each byte controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d3 (h) ac k byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) ac k dummy command code ac k dummy byte count ac k byte 0 ac k byte 1 ack byte 2 ac k byte 3 ac k byte 4 ac k byte 5 ac k stop bit how to write:
10 ics9248-138 0342c?08/26/03 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) on the ics9248- 138 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
11 ics9248-138 0342c?08/26/03 pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. internal clocks are not running after the device is put in power down. when pd# is active low all clocks need to be driven to a low value and held prior to turning off the vcos and crystal. the power up latency needs to be less than 3 ms. the power down latency should be as short as possible but conforming to the sequence requirements shown below. the ref and 48mhz clocks are expected to be stopped in the low state as soon as possible. due to the state of the internal logic, stopping and holding the ref clock outputs in the low state may require more than one clock cycle to complete. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248 device). 2. as shown, the outputs stop low on the next falling edge after pd# goes low. 3. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside this part. 4. the shaded sections on the vco and the crystal signals indicate an active clock. 5. diagrams shown with respect to 133mhz. similar operation when cpu is 100mhz. cpuclk 3v66 pciclk vco crystal pd#
12 ics9248-138 0342c?08/26/03 ordering information ics9248 y f-138 designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f - ppp - t index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n a 0808 variations min max min max 48 15.75 16.00 .620 .630 10-0034 0.635 basic 0.025 basic common dimensions in millimeters in inches common dimensions reference doc.: jedec publication 95, mo-118 300 mil ssop n see variations see variations d mm. d (inch) symbol see variations see variations
document search | package search | parametric search | cross reference search | green & rohs | calculators | thermal data | reliability & quality | military global sites email | print contact idt | investors | press search entire site home > products > timing solutions > pc-notebook-server clocks > clock synthesizer by chipset vendor > desktop chipsets > 9248-138 a dd to m y idt [ ? ] 9248-138 (desktop chipsets) description 810/810e and solano type chipset. market group pc clock additional info 810 and solano chipset - the ics9248-138 is the single chip cloc k solution for designs using the 810/810e and solano style chip set. it provides all necessary clock signals for such a system. spread spectrum may be enabled through i2c programming. spread spectrum typically re duces system emi by 8db to 10db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9248-138 employs a proprietary closed loop design, wh ich tightly controls the per centage of spreading over process and temperature varia tions. ? 2- cpus @ 2.5v ? 9 - sdram @ 3.3v, including 1 free running ? 7 - pciclk @ 3.3v ? 1 - ioapic @ 2.5v, ? 3 - 3v66mhz @ 3.3v ? 2 - 48mhz, @ 3.3v fixed. ? 1 - 24/48mhz, @3.3v selectable by i2c ? 1 - ref @v3.3v, 14.318mhz. you may also like... related orderable parts attributes 9248bf-138 9248bf-138lf 9248bf-138lft 9248bf-138t voltage 3.3 v (pv48) 3.3 v (pvg48) 3.3 v (pvg48) 3.3 v (pv48) package ssop 48 ssop 48 ssop 48 ssop 48 speed na na na na temperature c c c c status active active active active sample yes yes no no minimum order quantity 90 90 1000 1000 factory order increment 30 30 1000 1000 related documents type title size revision date datasheet 9248-138 datasheet 115 kb 03/23/2006 model - ibis 9248-138 ibis model 280 kb 03/23/2006 pa g e 1 of 2 08-jun-2007 mhtml:file://c:\9248-138.mh t
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